The technology described herein relates to display controllers for data processing systems.
As is known in the art, in data processing systems, an image that is to be displayed to a user is processed by the data processing system for display. The image for display is typically processed by a number of processing stages before it is displayed to the user. For example, an image will be processed by a so called “display controller” of a display for display.
Typically, the display controller will read an output image to be displayed from a so called “frame buffer” in memory which stores the image as a data array (e.g. by internal Direct Memory Access (DMA)) and provide the image data appropriately to the display (e.g. via a pixel pipeline) (which display may, e.g., be a screen or printer). The output image is stored in the frame buffer in memory, e.g. by a graphics processor, when it is ready for display and the display controller will then read the frame buffer and provide it to the display for display.
The display controller processes the image from the frame buffer to allow it to be displayed on this display. This processing includes appropriate display timing functionality (e.g. it is configured to send pixel data to the display with appropriate horizontal and vertical blanking periods), to allow the image to be displayed on the display correctly.
As is known in the art, the frame buffer itself is usually stored in so called “main” memory of the system in question, and that is therefore external to the display device and to the display controller. The reading of data from the frame buffer for display can therefore consume a relatively significant amount of power and memory bandwidth.
Many known electronic devices and systems use and display plural windows (or surfaces) displaying information on their display screen, such as video, a graphical user interface, etc.
A common way of providing such windows is to use a compositing window system, in which individual input windows (surfaces) are combined appropriately (i.e. composited) and the result is written out to the frame buffer, which is then read by the display controller for display.
An example of this composition process is shown in FIG. 1. In this process, input surfaces are generated by a video codec 1 and graphics processing unit 2, and stored in main memory 3 (e.g. frame buffer 0, 1 and 2). The stored surfaces are read and passed to a composition engine 4 which combines the input surfaces to generate a composited output frame. In the illustrated example, the composition engine 4 also performs colour space conversion (from YUV to RGB) and scaling operations on the input surface from video codec 1. The composited output frame is stored in main memory 3 (e.g. frame buffer 3). The stored composited output frame is read from the memory 3 by display controller 5, which sends the composited output frame to a local display 6 for display.
A conventional media processing system is shown in FIG. 2. This comprises a central processing unit (CPU) 7, graphics processing unit (GPU) 2, video codec 1, composition engine 4, display controller 5 and a memory controller 8. As shown in FIG. 2, these communicate via an interconnect 9 and have access to off-chip main memory 3. The composition engine 4 generates the composited output frame from one or more input surfaces (e.g. generated by the GPU 2 and/or video codec 1) and the composited output frame is then stored, via the memory controller 8, in a frame buffer in the off-chip memory 3. The display controller 5 then reads the composited output frame from the frame buffer in the off-chip memory 3 via the memory controller 8 and sends it to a display for display.
The Applicants believe that there remains scope for improvements to display controllers.
Like reference numerals are used for like components throughout the drawings, where appropriate.